1. Field of the Invention
This invention relates to a display apparatus wherein a thin film transistor as a switching device is formed on a transparent insulating substrate, a driving method for the display apparatus, and an electronic apparatus.
2. Description of the Related Art
A display apparatus, for example, a liquid crystal display apparatus wherein a liquid crystal cell is used as a display element or an electro-optical element is an image display apparatus wherein such pixels are arrayed in a matrix and an output image is displayed through a liquid crystal display face.
The liquid crystal display apparatus has features that it is slim and that it is low in power consumption. Making most of the features, the liquid crystal display apparatus is applied to various electronic apparatus such as, for example, personal digital assistants (PDA), portable telephone sets, digital cameras, video cameras and personal computers.
FIGS. 1A to 1C shows an example of a popular liquid crystal display apparatus and gate pulse waveforms of the liquid crystal display apparatus.
Referring first to FIG. 1A, the liquid crystal display apparatus 1 shown includes an effective pixel section 2, a vertical driving circuit (VDRV) 3 and a horizontal driving circuit (HDRV) 4.
The effective pixel section 2 has a plurality of pixel circuits 21 arrayed in a matrix.
Each of the pixel circuits 21 includes a thin film transistor TFT 22 serving as a switching device, a liquid crystal cell 23, and a holding capacitor 24. The liquid crystal cell 23 is connected at the pixel electrode thereof to the drain electrode or the source electrode of the TFT 22. The holding capacitor 24 is connected at one electrode thereof to the drain electrode of the TFT 22.
The pixel circuits 21 are connected to gate lines 5-l to 5-m wired along a pixel array direction for the individual rows and signal lines 6-1 to 6-n wired along the other pixel array direction for the individual columns.
The gate electrodes of the TFTs 22 of the pixel circuits 21 are individually connected to same ones of the gate lines 5-1 to 5-m in a unit of a row. The source electrodes or the drain electrodes of the pixel circuits 21 are individually connected to same ones of the signal lines 6-1 to 6-n in a unit of a column.
Further, in each of the pixel circuits 21, the liquid crystal cell 23 is connected at the pixel electrode thereof to the drain electrode of the TFT 22 and at the opposing electrode thereof to a common line 7. The holding capacitor 24 is connected between the drain electrode of the TFT 22 and the common line 7.
The common line 7 is connected to receive, as a common voltage Vcom, a predetermined ac voltage from a VCOM circuit not shown formed integrally with a driving circuit and so forth on a glass substrate.
The gate lines 5-1 to 5-m are individually driven by the vertical driving circuit 3, and the signal lines 6-1 to 6-n are individually driven by the horizontal driving circuit 4.
The vertical driving circuit 3 receives a vertical start signal VST, a vertical clock Vclk and an enable signal ENAB and scans in a vertical direction, that is, in a direction of a row for each one field period to successively select the pixel circuits 21 connected to the gate lines 5-1 to 5-m in a unit of a row.
In particular, when a scanning pulse Gp1 is applied from the vertical driving circuit 3 to the scanning line 5-1, the pixels in the columns in the first row are selected, and when another scanning pulse Gp2 is applied to the scanning line 5-2, the pixels in the columns in the second row are selected. Thereafter, gate pulses GP3, . . . , Gpm are successively applied to the gate lines or scanning lines 5-3, . . . , 5-m similarly, respectively.
Gate buffers 8-1 to 8-m are provided at the output stage of a gate pulse Gp to the vertical driving circuit 3 to the gate lines 5-1 to 5-m, respectively.
FIG. 1B shows an example of a waveform at the output stage of the gate buffer 8-m to the gate line 5-m after gate buffering of the gate pulse Gpm.
FIG. 1C shows an example of a waveform at a wire terminal portion of the gate line 5-m of the gate pulse Gpm.
The horizontal driving circuit 4 receives a horizontal start pulse Hst which is produced from a clock generator not shown and indicates starting of horizontal scanning and horizontal clocks Hclk of the opposite phases to each other which are used as a reference for horizontal scanning. Then, the horizontal driving circuit 4 generates a sampling pulse.
The horizontal driving circuit 4 successively samples image data R (red), G (green) and B (blue) inputted thereto in response to the sampling pulse generated thereby and supplies the sampled image data as data signals to be written into the pixel circuits 21 to the signal lines 6-1 to 6-n. 
The horizontal driving circuit 4 divides the signal lines 6-1 to 6-n into a plurality of groups and includes signal drivers 41 to 44 corresponding to the individual groups.
While the liquid crystal display apparatus 1 shown in FIG. 1 has a basic configuration, a large number of techniques have been proposed regarding gate line driving by such a vertical driving circuit 3 as described above and signal line driving by such a horizontal driving circuit 4 as described above. Such techniques are disclosed, for example, in Japanese Patent No. 3,276,996 (hereinafter referred to as Patent Document 1), Japanese Patent laid-Open No. 2007-52370 (hereinafter referred to as Patent Document 2), Japanese Patent No. 3,270,485 (hereinafter referred to as Patent Document 3), Japanese Patent Laid-Open No. 2006-78505 (hereinafter referred to as Patent Document 4), Japanese Patent Laid-Open No. 2005-148424 (hereinafter referred to as Patent Document 5), and Japanese Patent Laid-Open No. 2005-148425 (hereinafter referred to as Patent Document 6).